Yes, cache on a 6502-class CPU.
X65 now has a 64 kB L2 cache implemented in the RP2350’s internal SRAM,
sitting between the 65816 and external PSRAM.
PSRAM is relatively slow and was the main CPU bottleneck.
RP2350 SRAM runs at full MCU speed with no wait states,
so cache hits let the 65816 run as fast as it possibly can.
The RP2350 already acts as a bridge between the 65816’s 8-bit parallel bus
and the serial PSRAM interface. Adding caching is a natural extension of that role:
CPU (8-bit) ⇄ RP2350 [64 kB L2 SRAM] ⇄ PSRAM (8 MB)
64 kB is enough to hold the full working set of a typical task,
which significantly reduces PSRAM traffic.
I also evaluated the RP2350’s built-in QSPI XIP cache. It is slightly faster,
but limited to 16 kB. Both cache implementations are selectable
via a compile-time switch, so they can be compared on real workloads
once the new hardware revision is ready.